Programmable logic devices (PLDs) are a well-known type of IC that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (FPGA), typically includes an array of programmable tiles. These programmable tiles comprise various types of logic blocks, which can include, for example, input/output blocks (IOBs), configurable logic blocks (CLBs), dedicated random access memory blocks (BRAM), multipliers, digital signal processing blocks (DSPs), processors, clock managers, delay lock loops (DLLs), and so forth.
Each programmable tile typically includes both programmable interconnect and programmable logic. The programmable interconnect typically includes a large number of interconnect lines of varying lengths interconnected by programmable interconnect points (PIPs). The programmable logic implements the logic of a user design using programmable elements that can include, for example, function generators, registers, arithmetic logic, and so forth.
The programmable interconnect and programmable logic are typically programmed by loading a stream of configuration data into internal configuration memory cells that define how the programmable elements are configured. The configuration data can be read from memory (e.g., from an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
FIG. 1 is a simplified illustration of an exemplary FPGA. The FPGA of FIG. 1 includes an array of configurable logic blocks (CLBs 101-116) interconnected by a programmable interconnect structure that includes horizontal interconnect lines 120 and vertical interconnect lines 130.
Programmable ICs include many structures designed to support the programmable nature of the devices, e.g., configuration logic, configuration memory cells, control logic, and so forth. (The term “programmable ICs” as used herein includes but is not limited to FPGAs, mask programmable devices, Programmable Logic Devices (PLDs), and devices in which only a portion of the logic is programmable.) Therefore, a programmable IC, when programmed to implement a user design, may consume more power than a custom-designed IC that performs the same functions. Reduced power consumption is desirable to increase battery life, reduce operating temperatures, and improve reliability, for example. Therefore, programmable ICs are typically designed using various techniques having the object of reducing power consumption.
For example, FIG. 2 illustrates one known method of reducing power consumption in a programmable IC. Similar to FIG. 1, the FPGA of FIG. 2 includes an array of CLBs 201-216 interconnected by horizontal and vertical interconnect lines (220 and 230, respectively). However, in the FPGA of FIG. 2, each CLB includes a Power Management Block (PMB) that optionally turns off or reduces power to the CLB. Thus, power can be turned off or reduced when the CLB (or the entire FPGA) is not in use, thereby reducing the power consumption of the FPGA when the CLB is inactive.
The technique shown in FIG. 2 comes at a price, however. Reduced power consumption means reduced speed, and vice versa. The design of a PMB can significantly affect the performance of the IC, e.g., resulting in as much as a 1000× power difference and a 10× speed difference. Further, there is no one fixed PMB design that will suit all markets. For example, certain battery-operated devices may require very low power (e.g., in the microwatt range) but have a fairly low performance need (e.g., below 20 megahertz (MHz)), consumer electronics may require modest power (milliwatts) and modest performance (e.g., below 100 MHz), while high-speed data processing applications may have a generous power budget (e.g., several watts) but require very high performance (e.g., greater than 200 MHz).
Therefore, in order to reduce power consumption without unnecessarily reducing the maximum operating speed of the IC, the PMB is typically carefully designed to meet the speed requirements of the particular application for which the IC will be used. Designing different PMBs to meet the needs of different markets increases the cost of the ICs. Redesigning one of the CLBs in FIG. 2, for example, to meet the power and performance requirements of a particular application can significantly increase the development time and resources needed to bring the IC product to market.
It is desirable to simplify the process of providing an integrated circuit having a desired level of power reduction capability. It is further desirable to provide methods and structures for managing power in integrated circuits that facilitates the efficient development of a group of integrated circuits having different power and speed characteristics for market applications with different power and performance requirements.